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-Networking Line Cards
-HDI (High Density)
-Chip Evaluation Boards
-Probe & Load Boards
-RF / Analog / Mixed
-Flex & Rigid-Flex
-Backplanes
-Test Boards
-Miscellaneous
-10GBE, Gigabit Ethernet
-OC3 to 768
-Infiniband, PCIe, Rapid IO,
Hypertransport, Xaui, LVDS
-DDR 2 & 3
-XDR2
-Fibre Channel
-QDR2
-PCB Layout (12 Gbps+)
-Via / Connector Modeling
-Design Guidelines Creation
-Stack-up Creation
-DFM / DFT
-Signal Integrity Analysis
-Routing ONLY Services
SIGNAL INTEGRITY
- Hspice / IBIS
CAD
- Cadence Allegro
- Mentor Expedition
SCHEMATIC
- Ansoft HFSS
- Mentor Pads PCB
- Orcad
-Netlist
-Pre-Placement Drawing
-Statement of Work
-Component Datasheets
-Constraint Data
-PCB Layout Checklist
-BOM (Excel format)
-Mechanical Outline
-PCB Layout Sign-off Form
-Cadence Allegro Viewer
-Pads PCB Viewer
-IPC Land Pattern Viewer
-Allegro, Expedition, Pads
-IPC PCB Standards
-Mentor Expedition Viewer
-IPC Naming Conventions